10861

NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems

Roberto Ammendola, Andrea Biagioni, Riccardo Fantechi, Ottorino Frezza, Gianluca Lamanna, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Felice Pantaleo, Roberto Piandani, Luca Pontisso, Davide Rossetti, Francesco Simula, Marco Sozzi, Laura Tosoratto, Piero Vicini
INFN, Rome – Tor Vergata, Italy
arXiv:1311.1010 [physics.ins-det], (5 Nov 2013)

@article{2013arXiv1311.1010A,

   author={Ammendola}, R. and {Biagioni}, A. and {Fantechi}, R. and {Frezza}, O. and {Lamanna}, G. and {Lo Cicero}, F. and {Lonardo}, A. and {Stanislao Paolucci}, P. and {Pantaleo}, F. and {Piandani}, R. and {Pontisso}, L. and {Rossetti}, D. and {Simula}, F. and {Sozzi}, M. and {Tosoratto}, L. and {Vicini}, P.},

   title={"{NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems}"},

   journal={ArXiv e-prints},

   archivePrefix={"arXiv"},

   eprint={1311.1010},

   primaryClass={"physics.ins-det"},

   keywords={Physics – Instrumentation and Detectors},

   year={2013},

   month={nov},

   adsurl={http://adsabs.harvard.edu/abs/2013arXiv1311.1010A},

   adsnote={Provided by the SAO/NASA Astrophysics Data System}

}

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We implemented the NaNet FPGA-based PCI2 Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.
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