11264

High-performance and Embedded Systems for Cryptography

Samuel Freitas Antao
Universidade de Lisboa, Instituto Superior Tecnico
Universidade de Lisboa, 2013
@phdthesis{Antao2013phd,

   author={Ant~{a}o, Samuel},

   keywords={Algorithms,Application-Specific Integrated Circuit (ASIC),Elliptic Curve Cryptography,Embedded,Field Programmable Gate Array (FPGA),Graphics Processing Unit (GPU),Modular Arithmetic,Parallel,Residue Number System (RNS),Rivest-Shamir-Adleman (RSA),Systems},

   pages={147},

   school={Instituto Superior T’{e}cnico – University of Lisbon},

   title={High-performance and Embedded Systems for Cryptography},

   type={PhD},

   year={2013}

}

Download Download (PDF)   View View   Source Source   

453

views

This thesis addresses the design of cryptographic accelerators, ranging from the embedded system to the high-performance computing device. New techniques are proposed to allow several cryptographic algorithms to be computed by the same target. Therefore, flexibility (to support several algorithms) and scalability (to extend the features of a designed accelerator) are two keywords in all the contributions of this thesis. Among these contributions is the design of a cryptographic accelerator tailored for Field Programming Gate Arrays (FPGAs) able to support the Advanced Encryption Standard (AES) and Elliptic Curve (EC) cryptography. The desired speed-cost tradeoff can be easily tuned through reconfiguration due to the modular design of the accelerator. Another technique herein proposed is the utilization of the Residue Number System (RNS) to expose parallelism in cryptographic algorithms. This technique enables the design of efficient programmable accelerators for devices capable of providing a large degree of parallelism, namely Graphical Processing Units (GPUs). A thorough evaluation and design of massive parallel accelerators for modular arithmetic (the arithmetic that underlie many cryptographic algorithms) is accomplished in this thesis. This leverages the proposal of the Computing with the Residue Number System Framework (CRNS), which aims at the automatic implementation of fully functional cryptograhic accelerators based on FPGAs or GPUs.
VN:F [1.9.22_1171]
Rating: 0.0/5 (0 votes cast)

* * *

* * *

Like us on Facebook

HGPU group

142 people like HGPU on Facebook

Follow us on Twitter

HGPU group

1221 peoples are following HGPU @twitter

Featured events

* * *

Free GPU computing nodes at hgpu.org

Registered users can now run their OpenCL application at hgpu.org. We provide 1 minute of computer time per each run on two nodes with two AMD and one nVidia graphics processing units, correspondingly. There are no restrictions on the number of starts.

The platforms are

Node 1
  • GPU device 0: AMD/ATI Radeon HD 5870 2GB, 850MHz
  • GPU device 1: AMD/ATI Radeon HD 6970 2GB, 880MHz
  • CPU: AMD Phenom II X6 @ 2.8GHz 1055T
  • RAM: 12GB
  • OS: OpenSUSE 13.1
  • SDK: AMD APP SDK 2.9
Node 2
  • GPU device 0: AMD/ATI Radeon HD 7970 3GB, 1000MHz
  • GPU device 1: nVidia GeForce GTX 560 Ti 2GB, 822MHz
  • CPU: Intel Core i7-2600 @ 3.4GHz
  • RAM: 16GB
  • OS: OpenSUSE 12.2
  • SDK: nVidia CUDA Toolkit 6.0.1, AMD APP SDK 2.9

Completed OpenCL project should be uploaded via User dashboard (see instructions and example there), compilation and execution terminal output logs will be provided to the user.

The information send to hgpu.org will be treated according to our Privacy Policy

HGPU group © 2010-2014 hgpu.org

All rights belong to the respective authors

Contact us: