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Developmental Directions in Parallel Accelerators

K.A. Hawick, D.P. Playne
Computer Science, Institute of Natural and Mathematical Sciences, Massey University, Albany North, Shore 102-904, Auckland, New Zealand
Twelfth Australasian Symposium on Parallel and Distributed Computing (AusPDC 2014), Australian Computer Society, Inc., 2014

@article{hawick2014developmental,

   title={Developmental Directions in Parallel Accelerators},

   author={Hawick, K.A. and Playne, D.P.},

   year={2014}

}

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Parallel accelerators such as massively-cored graphical processing units or many-cored co-processors such as the Xeon Phi are becoming widespread and affordable on many systems including blade servers and even desktops. The use of a single such accelerator is now quite common for many applications, but the use of multiple devices and hybrid combinations is still very unusual. The main barrier to greater uptake of multiple accelerators in applications is still the software ecosystem and in particular the interoperability limitations of setting up appropriate software stacks for novel accelerator combinations. We present some benchmark results for various multiple and hybrid accelerator combinations using some up to date modern devices and discuss feasible developmental directions for high computational performance scientific applications software to use them. We compare results with equivalent benchmarks on conventional multi-cored CPUs.
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