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GPU-based Acceleration of System-level Design Tasks

Unmesh Bordoloi, Samarjit Chakraborty
VERIMAG, Centre Equation – 2, avenue de Vignate, 38610, GIERES
International Journal of Parallel Programming (16 January 2010)

@article{bordoloi2010gpu,

   title={GPU-based Acceleration of System-level Design Tasks},

   author={Bordoloi, U.D. and Chakraborty, S.},

   journal={International Journal of Parallel Programming},

   volume={38},

   number={3},

   pages={225–253},

   issn={0885-7458},

   year={2010},

   publisher={Springer}

}

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Many system-level design tasks (e.g., high-level timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-hard). As a result, they involve high running times even for mid-sized problems. In this paper we explore the possibility of using commodity graphics processing units (GPUs) to accelerate such tasks that commonly arise in the electronic design automation (EDA) domain. We demonstrate this idea via two detailed case studies. The first explores the possibility of using GPUs to speedup standard schedulability analysis problems. The second proposes a GPU-based engine for a general hardware/software design space exploration problem. Not only do these problems commonly arise in the embedded systems domain, their computational kernels turn out to be variants of a combinatorial optimization problem
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