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Power Efficient Large Matrices Multiplication by Load Scheduling on Multi-core and GPU Platform with CUDA

DaQi Ren, Reiji Suda
Department of Computer Science, University of Tokyo, Tokyo, Japan
Computational Science and Engineering, IEEE International Conference on, Vol. 1 (31 August 2009), pp. 424-429.

@conference{suda2009power,

   title={Power Efficient Large Matrices Multiplication by Load Scheduling on Multi-core and GPU Platform with CUDA},

   author={Suda, R.},

   booktitle={Computational Science and Engineering, 2009. CSE’09. International Conference on},

   volume={1},

   pages={424–429},

   year={2009},

   organization={IEEE}

}

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Power efficiency is one of the most important issues in high performance computing (HPC) interrelated to both software and hardware. Power dissipation of a program lies on algorithm design and power features of the computer components on which the program runs. In this work, we measure and model the power consumption of large matrices multiplication on multi-core CPU and GPU platform. By incorporating major physical power constrains of hardware components with the analysis of program execution behaviors, we approach to save the overall power consumption by using multithreading CPU to control two GPU devices computing in parallel synchronously. By implementing above method on real system, we show that it can save 22% of energy and speedup the kernel execution time by 71%, compare with solving the same large matrices multiplication using single CPU and GPU combination.
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