The Sixth International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2015

June 1-2, 2015
Boston MA, USA

The HEART symposium is an international forum on state-of-the-art research in high-performance and power-efficient computing using accelerator technologies such as FPGAs, GPGPUs, and/or specialized accelerators. The fifth edition of HEART will take place in Boston MA, USA.
The Sixth International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation. Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:

Architectures and systems:
Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices
Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation
Reconfigurable and configurable hardware and systems including IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing
Custom computing system for domain-specific applications such as Big-data, multimedia, bioinformatics, cryptography, and more
Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devices

Software and applications:
Novel applications of high-performance computing and Big-data processing with efficientacceleration and custom computing
System software, compilers and programming languages for efficient accelerationsystems / platforms, including many-core processors, GPUs, FPGAs and otherreconfigurable /custom processors
Run-time techniques for acceleration, including Just-in-Time compilation and dynamicpartial-reconfiguration
Performance evaluation and analysis for efficient acceleration
High-level synthesis and design methodologies for heterogeneous, reconfigurable and/orcustom processors/systems

In order to encourage open discussion on future directions, the program committee will provide higher priority for papers that present highly innovative and challenging ideas.

We are planning to organize special sessions on HPC, Big data, and Dynamic Reconfiguration. When submitting a paper, please select topic(s) if the paper is related to them. Note that regardless of the selection of special session topic(s), your paper will undergo the same peer-review process as the main technical track.

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