FPGA-Based Design of Numerical Algorithms for Kernel Density Estimation Using High Level Synthesis Approach

Artur Gramacki, Marek Sawerwain, Jaroslaw Gramacki
Institute of Control and Computation Engineering, University of Zielona Gora, ul. Licealna 9, Zielona Gora 65-417, Poland
arXiv:1505.02100 [cs.OH], (8 May 2015)

   title={FPGA-Based Design of Numerical Algorithms for Kernel Density Estimation Using High Level Synthesis Approach},

   author={Gramacki, Artur and Sawerwain, Marek and Gramacki, Jaroslaw},






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FPGA technology can offer significantly higher performance at much lower power than is available from CPUs and GPUs in many computational problems. Unfortunately, programming for FPGA (using hardware description languages, HDL) is a difficult and not-trivial task and is not intuitive for C/C++/Java programmers. To bring the gap between programming effectiveness and difficulty the High Level Synthesis (HLS) approach is promoting by many FPGA vendors. Nowadays, time-intensive calculations are mainly performed on GPU/CPU architectures, but can also be successfully performed using HLS approach. In the paper we implement a selected numerical algorithm (bandwidth selection for kernel density estimators, KDE) using HLS and show techniques which were used to optimise the final FPGA implementation.
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