14427

Bufferless NOC Simulation of Large Multicore System on GPU Hardware

Navin Kumar, Aryabartta Sahu
Department of Computer Science and Engineering, Indian Institute of Technology Guwahati
arXiv:1508.03235 [cs.DC], (12 Aug 2015)

@article{kumar2015bufferless,

   title={Bufferless NOC Simulation of Large Multicore System on GPU Hardware},

   author={Kumar, Navin and Sahu, Aryabartta},

   year={2015},

   month={aug},

   archivePrefix={"arXiv"},

   primaryClass={cs.DC}

}

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Last level cache management and core interconnection network play important roles in performance and power consumption in multicore system. Large scale chip multicore uses mesh interconnect widely due to scalability and simplicity of the mesh interconnection design. As interconnection network occupied significant area and consumes significant percent of system power, bufferless network is an appealing alternative design to reduce power consumption and hardware cost. We have designed and implemented a simulator for simulation of distributed cache management of large chip multicore where cores are connected using bufferless interconnection network. Also, we have redesigned and implemented the our simulator which is a GPU compatible parallel version of the same simulator using CUDA programming model. We have simulated target large chip multicore with up to 43,000 cores and achieved up to 25 times speedup on NVIDIA GeForce GTX 690 GPU over serial simulation.
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