Fault Table Computation on GPUs

Kanupriya Gulati, Sunil Khatri
Department of ECE, Texas A&M University, College Station, TX 77843, USA
Journal of Electronic Testing, Volume 26, Number 2, 195-209 (12 February 2010)


   title={Fault Table Computation on GPUs},

   author={Gulati, K. and Khatri, S.P.},

   journal={Journal of Electronic Testing},








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In this paper, we explore the implementation of fault table generation on a Graphics Processing Unit (GPU). A fault table is essential for fault diagnosis and fault detection in VLSI testing and debug. Generating a fault table requires extensive fault simulation, with no fault dropping, and is extremely expensive from a computational standpoint. Fault simulation is inherently parallelizable, and the large number of threads that a GPU can operate on in parallel can be employed to accelerate fault simulation, and thereby accelerate fault table generation. Our approach, called GFTABLE, employs a pattern parallel approach which utilizes both bit-parallelism and thread-level parallelism. Our implementation is a significantly modified version of FSIM, which is pattern parallel fault simulation approach for single core processors. Like FSIM, GFTABLE utilizes critical path tracing and the dominator concept to reduce runtime. Further modifications to FSIM allow us to maximally harness the GPU
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