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An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing

Jung-Wook Park, Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim, Charles C. Weems
Department of Computer Science, C532, Yonsei University, 134 Shinchon-dong Seoul, 120-749, Republic of Korea
Journal of Parallel and Distributed Computing, Volume 70, Issue 11, November 2010, Pages 1110-1118 (14 July 2010)

@article{park2010instruction,

   title={An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing},

   author={Park, J.W. and Yang, H.M. and Park, G.H. and Kim, S.D. and Weems, C.C.},

   journal={Journal of Parallel and Distributed Computing},

   issn={0743-7315},

   year={2010},

   publisher={Elsevier}

}

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In order to guarantee both performance and programmability demands in 3D graphics applications, vector and multithreaded SIMD architectures have been employed in recent graphics processing units. This paper introduces a novel instruction-systolic array architecture, which transfers an instruction stream in a pipelined fashion to efficiently share the expensive functional resources of a graphics processor. Specifically, cache misses and dynamic branches can cause additional latencies and complicated management in these parallel architectures. To address this problem, we combine a systolic execution scheme with on-demand warp activation that handles cache miss latency and branch divergence efficiently without significantly increasing hardware resources, either in terms of logic or register space. Simulation indicates that the proposed architecture offers 25% better performance than a traditional SIMD architecture with the same resources, and requires significantly fewer resources to match the performance of a typical modern vector multi-threaded GPU architecture.
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