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Jitter analysis of PLL-generated clock propagation using Jitter Mitigation techniques with laser voltage probing

Joy Y. Liao, Tung Ton, Nathan Slattengren, Steven Kasapi, William K. Lo, Howard L. Marks, Yin S. Ng, Ted Lundquist
NVIDIA Corporation, 2701 San Tomas Expressway, Santa Clara, CA 95050, USA
Microelectronics Reliability, Volume 49, Issues 9-11, September-November 2009, Pages 1127-1131

@article{liao2009jitter,

   title={Jitter analysis of PLL-generated clock propagation using Jitter Mitigation techniques with laser voltage probing},

   author={Liao, J.Y. and Ton, T. and Slattengren, N. and Kasapi, S. and Lo, W.K. and Marks, H.L. and Ng, Y.S. and Lundquist, T.},

   journal={Microelectronics Reliability},

   volume={49},

   number={9-11},

   pages={1127–1131},

   issn={0026-2714},

   year={2009},

   publisher={Elsevier}

}

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A new Jitter Mitigation feature in the latest generation laser voltage probing (LVP) tool effectively removes PLL jitter from LVP waveforms [Ng Yin S, Lo W, Wilsher K. Next generation laser voltage probing. In: Proceeding, international symposium on testing and failure analysis; 2008. p. 249]. It facilitates the probing of phase-locked loop (PLL) driven circuitry inside of integrated circuits (ICs). In particular, it allows the detection of small amounts of excess jitter that would normally be masked by the much larger jitter of the PLL. To demonstrate the practical application of this Jitter Mitigation feature, we report on the jitter analysis of a PLL-generated clock signal as it propagates, through buffers and logic circuitry, to an external I/O pad of an IC. The IC was a 0.9 V, 65 nm technology graphics processing unit (GPU). The analysis was to determine where excess jitter was introduced into the clock path when the GPU was electrically stressed. Details of the jitter analysis, including Jitter Mitigation methodology, probing setup, and results of the timing measurements, will be presented in this paper.
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