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A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks

Yixing Li, Zichuan Liu, Kai Xu, Hao Yu, Fengbo Ren
School of Computing, Informatics, Decision Systems Engineering, Arizona State University, Tempe, USA
arXiv:1702.06392 [cs.DC], (20 Feb 2017)

@article{li2017tops,

   title={A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks},

   author={Li, Yixing and Liu, Zichuan and Xu, Kai and Yu, Hao and Ren, Fengbo},

   year={2017},

   month={feb},

   archivePrefix={"arXiv"},

   primaryClass={cs.DC}

}

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FPGA-based hardware accelerators for convolutional neural networks (CNNs) have obtained great attentions due to their higher energy efficiency than GPUs. However, it is challenging for FPGA-based solutions to achieve a higher throughput than GPU counterparts. In this paper, we demonstrate that FPGA acceleration can be a superior solution in terms of both throughput and energy efficiency when a CNN is trained with binary constraints on weights and activations. Specifically, we propose an optimized accelerator architecture tailored for bitwise convolution and normalization that features massive spatial parallelism with deep pipelines stages. Experiment results show that the proposed architecture is 8.3x faster and 75x more energy-efficient than a Titan X GPU for processing online individual requests (in small batch size). For processing static data (in large batch size), the proposed solution is on a par with a Titan X GPU in terms of throughput while delivering 9.5x higher energy efficiency.
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