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A Study of Complex Deep Learning Networks on High Performance, Neuromorphic, and Quantum Computers

Thomas E. Potok, Catherine Schuman, Steven R. Young, Robert M. Patton, Federico Spedalieri, Jeremy Liu, Ke-Thia Yao, Garrett Rose, Gangotree Chakma
Oak Ridge National Laboratory
arXiv:1703.05364 [cs.NE], (15 Mar 2017)

@article{potok2017study,

   title={A Study of Complex Deep Learning Networks on High Performance, Neuromorphic, and Quantum Computers},

   author={Potok, Thomas E. and Schuman, Catherine and Young, Steven R. and Patton, Robert M. and Spedalieri, Federico and Liu, Jeremy and Yao, Ke-Thia and Rose, Garrett and Chakma, Gangotree},

   year={2017},

   month={mar},

   archivePrefix={"arXiv"},

   primaryClass={cs.NE}

}

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Current Deep Learning approaches have been very successful using convolutional neural networks (CNN) trained on large graphical processing units (GPU)-based computers. Three limitations of this approach are: 1) they are based on a simple layered network topology, i.e., highly connected layers, without intra-layer connections; 2) the networks are manually configured to achieve optimal results, and 3) the implementation of neuron model is expensive in both cost and power. In this paper, we evaluate deep learning models using three different computing architectures to address these problems: quantum computing to train complex topologies, high performance computing (HPC) to automatically determine network topology, and neuromorphic computing for a low-power hardware implementation. We use the MNIST dataset for our experiment, due to input size limitations of current quantum computers. Our results show the feasibility of using the three architectures in tandem to address the above deep learning limitations. We show a quantum computer can find high quality values of intra-layer connections weights, in a tractable time as the complexity of the network increases; a high performance computer can find optimal layer-based topologies; and a neuromorphic computer can represent the complex topology and weights derived from the other architectures in low power memristive hardware.
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