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Design Exploration of AES Accelerators on FPGAs and GPUs

Vincenzo Conti, Salvatore Vitabile
Faculty of Engineering and Architecture, University of Enna Kore, Enna, Italy
Journal of Telecommunications and Information Technology, 1, 2017

@article{conti2017design,

   title={Design Exploration of AES Accelerators on FPGAs and GPUs},

   author={Conti, Vincenzo and Vitabile, Salvatore},

   year={2017}

}

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The embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems and an exhaustive analysis of the state of the art of all current performance with respect to architectures, design methodologies, test and applications could be very interesting. The Advanced Encryption Standard (AES), based on the well-known algorithm Rijndael, is designed to be easily implemented in hardware and software platforms. General purpose computing on graphics processing unit (GPGPU) is an alternative to reconfigurable accelerators based on FPGA devices. This paper presents a direct comparison between FPGA and GPU used as accelerators for the AES cipher. The results achieved on both platforms and their analysis has been compared to several others in order to establish which device is best at playing the role of hardware accelerator by each solution showing interesting considerations in terms of throughput, speedup factor, and resource usage. This analysis suggests that, while hardware design on FPGA remains the natural choice for consumer-product design, GPUs are nowadays the preferable choice for PC based accelerators, especially when the processing routines are highly parallelizable.
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