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Design of Hardware Accelerator for Lempel-Ziv 4 (LZ4) Compression

Sang Muk Lee, Ji Hoon Jang, Jung Hwan Oh, Ji Kwang Kim, Seung Eun Lee
Dept. of Electronic Engineering, Seoul National Univ. of Science and Technology 232 Gongreung-ro, Nowon-gu, Seoul, 139-743, Korea
IEICE Electronics Express, Article ID: 14.20170399, 2017

@article{lee2017design,

   title={Design of Hardware Accelerator for Lempel-Ziv 4 (LZ4) Compression},

   author={Lee, Sang Muk and Jang, Ji Hoon and Oh, Jung Hwan and Kim, Ji Kwang and Lee, Seung Eun},

   journal={IEICE Electronics Express},

   pages={14–20170399},

   publisher={The Institute of Electronics, Information and Communication Engineers},

   year={2017}

}

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Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65nm CMOS technology.
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