BLAS Comparison on FPGA, CPU and GPU

Srinidhi Kestur, John D. Davis, Oliver Williams
Dept. of Computer Science and Engineering, The Pennsylvania State University, University Park, PA 16802
In Proceedings of the 2010 IEEE Annual Symposium on VLSI (2010), pp. 288-293.


   title={BLAS Comparison on FPGA, CPU and GPU},

   author={Kestur, S. and Davis, J.D. and Williams, O.},

   booktitle={Proceedings of the 2010 IEEE Annual Symposium on VLSI},



   organization={IEEE Computer Society}


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High Performance Computing (HPC) or scientific codes are being executed across a wide variety of computing platforms from embedded processors to massively parallel GPUs. We present a comparison of the Basic Linear Algebra Subroutines (BLAS) using double-precision floating point on an FPGA, CPU and GPU. On the CPU and GPU, we utilize standard libraries on state-of-the-art devices. On the FPGA, we have developed parameterized modular implementations for the dot-product and Gaxpy or matrix-vector multiplication. In order to obtain optimal performance for any aspect ratio of the matrices, we have designed a high-throughput accumulator to perform an efficient reduction of floating point values. To support scalability to large data-sets, we target the BEE3 FPGA platform. We use performance and energy efficiency as metrics to compare the different platforms. Results show that FPGAs offer comparable performance as well as 2.7 to 293 times better energy efficiency for the test cases that we implemented on all three platforms.
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