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Larrabee: a many-core x86 architecture for visual computing

Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan
Intel Corporation
In SIGGRAPH ’08: ACM SIGGRAPH 2008 papers (2008), pp. 1-15

@conference{seiler2008larrabee,

   title={Larrabee: a many-core x86 architecture for visual computing},

   author={Seiler, L. and Carmean, D. and Sprangle, E. and Forsyth, T. and Abrash, M. and Dubey, P. and Junkins, S. and Lake, A. and Sugerman, J. and Cavin, R. and others},

   booktitle={ACM SIGGRAPH 2008 papers},

   pages={1–15},

   year={2008},

   organization={ACM}

}

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This paper presents a many-core visual computing architecture code named Larrabee, a new software rendering pipeline, a manycore programming model, and performance analysis for several applications. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector processor unit, as well as some fixed function logic blocks. This provides dramatically higher performance per watt and per unit of area than out-of-order CPUs on highly parallel workloads. It also greatly increases the flexibility and programmability of the architecture as compared to standard GPUs. A coherent on-die 2 nd level cache allows efficient inter-processor communication and high-bandwidth local data access by CPU cores. Task scheduling is performed entirely with software in Larrabee, rather than in fixed function logic. The customizable software graphics rendering pipeline for this architecture uses binning in order to reduce required memory bandwidth, minimize lock contention, and increase opportunities for parallelism relative to standard GPUs. The Larrabee native programming model supports a variety of highly parallel applications that use irregular data structures. Performance analysis on those applications demonstrates Larrabee’s potential for a broad range of parallel computation.
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