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Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors

Nachiket Kapre, Andre DeHon
Computer Science, California Institute of Technology, Pasadena CA 91125
International Conference on Field Programmable Logic and Applications, 2009. FPL 2009. p.65-72

@conference{kapre2009performance,

   title={Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors},

   author={Kapre, N. and DeHon, A.},

   booktitle={Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on},

   pages={65–72},

   issn={1946-1488},

   year={2009},

   organization={IEEE}

}

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Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor organizations for data-parallel, floating-point computation in SPICE model-evaluation. Our Verilog AMS compiler produces code for parallel evaluation of non-linear circuit models suitable for use in SPICE simulations where the same model is evaluated several times for all the devices in the circuit. Our compiler uses architecture specific parallelization strategies (OpenMP for multi-core, PThreads for Cell, CUDA for GPU, statically scheduled VLIW for FPGA) when producing code for these different architectures. We automatically explore different implementation configurations (e.g. unroll factor, vector length) using our performance-tuner to identify the best possible configuration for each architecture. We demonstrate speedups of 3- 182times for a Xilinx Virtex5 LX 330T, 1.3-33times for an IBM Cell, and 3-131times for an NVIDIA 9600 GT GPU over a 3 GHz Intel Xeon 5160 implementation for a variety of single-precision device models.
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