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Using Reconfigurable Logic to Optimise GPU Memory Accesses

Ben Cope, Peter Y. K. Cheung, Wayne Luk
Department of Electrical & Electronic Engineering, Imperial College London
Design, Automation and Test in Europe, 2008. DATE ’08, p.44-49

@conference{cope2008using,

   title={Using reconfigurable logic to optimise GPU memory accesses},

   author={Cope, B. and Cheung, P.Y.K. and Luk, W.},

   booktitle={Design, Automation and Test in Europe, 2008. DATE’08},

   pages={44–49},

   year={2008},

   organization={IEEE}

}

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Memory access patterns common in video processing algorithms, which are unsuited to the GPU (Graphics Processing Unit) memory system, are identified. We develop REDA (Reconfigurable Engine for Data Access) to improve GPU performance for such access patterns, by employing reconfigurable logic for address mapping. It is shown that a sixty times reduction in number of video memory accesses can be achieved for previously unsuited access patterns, with no detriment to well suited patterns. Surprisingly, memory access locality is also improved.
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