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A low-power handheld GPU using logarithmic arithmetic and triple DVFS power domains

Byeong-Gyu Nam, Jeabin Lee, Kwanho Kim, Seung Jin Lee, and Hoi-Jun Yoo
Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea
Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware, GH ’07

@conference{nam2007low,

   title={A low-power handheld GPU using logarithmic arithmetic and triple DVFS power domains},

   author={Nam, B.G. and Lee, J. and Kim, K. and Lee, S.J. and Yoo, H.J.},

   booktitle={Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware},

   pages={73–80},

   year={2007},

   organization={Eurographics Association}

}

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In this paper, a low-power GPU architecture is described for the handheld systems with limited power and area budgets. The GPU is designed using logarithmic arithmetic for power- and area-efficient design. For this GPU, a multifunction unit is proposed based on the hybrid number system of floating-point and logarithmic numbers and the matrix, vector, and elementary functions are unified into a single arithmetic unit. It achieves the single-cycle throughput for all these functions, except for the matrix-vector multiplication with 2-cycle throughput. The vertex shader using this function unit as its main datapath shows 49.3% cycle count reduction compared with the latest work for OpenGL transformation and lighting (TnL) kernel. The rendering engine uses also the logarithmic arithmetic for implementing the divisions in pipeline stages. The GPU is divided into triple dynamic voltage and frequency scaling power domains to minimize the power consumption at a given performance level. It shows a performance of 5.26Mvertices/s at 200MHz for the OpenGL TnL and 52.4mW power consumption at 60fps. It achieves 2.47 times performance improvement while reducing 50.5% power and 38.4% area consumption compared with the latest work.
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