2413

Evaluation and tuning of the Level 3 CUBLAS for graphics processors

S. Barrachina, M. Castillo, F. D. Igual, R. Mayo, E. S. Quintana-Orti
Departamento de Ingenieria y Ciencia de Computadores, Universidad Jaime I, Campus de Riu Sec, s/n 12.071 – Castellon, Espana
Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on (18 April 2008), pp. 1-8.

@conference{barrachina2008evaluation,

   title={Evaluation and tuning of the level 3 CUBLAS for graphics processors},

   author={Barrachina, S. and Castillo, M. and Igual, F.D. and Mayo, R. and Quintana-Orti, ES},

   booktitle={Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on},

   pages={1–8},

   issn={1530-2075},

   year={2008},

   organization={IEEE}

}

Download Download (PDF)   View View   Source Source   

580

views

The increase in performance of the last generations of graphics processors (GPUs) has made this class of platform a coprocessing tool with remarkable success in certain types of operations. In this paper we evaluate the performance of the Level 3 operations in CUBLAS, the implementation of BIAS for NVIDIA GPUs with unified architecture. From this study, we gain insights on the quality of the kernels in the library and we propose several alternative implementations that are competitive with those in CUBLAS. Experimental results on a GeForce 8800 Ultra compare the performance of CUBLAS and the new variants.
No votes yet.
Please wait...

* * *

* * *

HGPU group © 2010-2017 hgpu.org

All rights belong to the respective authors

Contact us: