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Hardware Accelerators for Cartesian Genetic Programming

Zdenek Vasicek and Lukas Sekanina
Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66 Brno, Czech Republic
Genetic Programming, Lecture Notes in Computer Science, 2008, Volume 4971/2008, 230-241

@article{vasicek2008hardware,

   title={Hardware accelerators for cartesian genetic programming},

   author={Vasicek, Z. and Sekanina, L.},

   journal={Genetic Programming},

   pages={230–241},

   year={2008},

   publisher={Springer}

}

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A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP). The accelerators contain a genetic engine which is reused in all applications. Candidate programs (circuits) are evaluated using application-specific virtual reconfigurable circuit (VRC) and fitness unit. Two types of VRCs are proposed. The first one is devoted for symbolic regression problems over the fixed point representation. The second one is designed for evolution of logic circuits. In both cases a significant speedup of evolution (30-40 times) was obtained in comparison with a highly optimized software implementation of CGP. This speedup can be increased by creating multiple fitness units.
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