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GPGPU-based Latency Insertion Method: Application to PDN simulations

Y. Inoue, T. Sekine, H. Asai
Grad. Sch. of Sci. & Technol., Shizuoka Univ., Hamamatsu, Japan
IEEE Electrical Design of Advanced Packaging & Systems Symposium, 2009. (EDAPS 2009)

@conference{inoue2009gpgpu,

   title={GPGPU-based Latency Insertion Method: Application to PDN simulations},

   author={Inoue, Y. and Sekine, T. and Asai, H.},

   booktitle={Electrical Design of Advanced Packaging & Systems Symposium, 2009.(EDAPS 2009). IEEE},

   pages={1–4},

   organization={IEEE}

}

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With the progress of high-density integration technology of the circuits, a variety of signal and power integrity problems have become serious and important for the electronic design. This paper describes the fast circuit simulation by GPGPU-LIM (GPGPU-based Latency Insertion Method). First, LIM is reviewed, which is a fast algorithm. Next, implementation of LIM on the general purpose computing on graphic processing unit (GPGPU) is shown. Furthermore, this method is applied to the simulation of power distribution networks (PDNs). Finally, it is confirmed that GPGPU-based LIM is very practical and efficient for the large-scale PDN simulations.
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