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Using GPU to Accelerate Cache Simulation

Wan Han, Gao Xiaopeng, Wang Zhiqiang, Li Yi
State Key Lab. of Virtual Reality Technol. & Syst., Beijing Univ. of Aeronaut. & Astronaut., Beijing, China
Parallel and Distributed Processing with Applications, 2009 IEEE International Symposium on

@conference{han2009using,

   title={Using gpu to accelerate cache simulation},

   author={Han, W. and Xiaopeng, G. and Zhiqiang, W. and Yi, L.},

   booktitle={2009 IEEE International Symposium on Parallel and Distributed Processing with Applications},

   pages={565–570},

   year={2009},

   organization={IEEE}

}

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Caches play a major role in the performance of high speed computer systems. Trace driven simulator is the most widely used method to evaluate cache architectures. However, as the cache design moves to more complicated architectures, along with the size of the trace is becoming larger and larger. Traditional simulation methods are no longer practical due to their long simulation cycles. Several techniques have been proposed to reduce the simulation time of sequential trace driven simulation. This paper considers the use of generic GPU to accelerate cache simulation which exploits set partitioning as the main source of parallelism. We develop more efficient parallel simulation techniques by introducing more knowledge into the Compute Unified Device Architecture (CUDA) on the GPU. Our experimental result shows that the new algorithm gains 2.76 times performance improvement compared to traditional CPU based sequential algorithm.
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