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A high-performance fault-tolerant software framework for memory on commodity GPUs

Naoya Maruyama, Akira Nukada, Satoshi Matsuoka
GSIC, Tokyo Institute of Technology, JST CREST
IEEE International Symposium on Parallel & Distributed Processing (IPDPS), 2010

@conference{maruyama2010high,

   title={A high-performance fault-tolerant software framework for memory on commodity GPUs},

   author={Maruyama, N. and Nukada, A. and Matsuoka, S.},

   booktitle={Parallel & Distributed Processing (IPDPS), 2010 IEEE International Symposium on},

   pages={1–12},

   issn={1530-2075},

   organization={IEEE}

}

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As GPUs are increasingly used to accelerate HPC applications by allowing more flexibility and programmability, their fault tolerance is becoming much more important than before when they were used only for graphics. The current generation of GPUs, however, does not have standard error detection and correction capabilities, such as SEC-DED ECC for DRAM, which is almost always exercised in HPC servers. We present a high-performance software framework to enhance commodity off-the-shelf GPUs with DRAM fault tolerance. It combines data coding for detecting bit-flip errors and checkpointing for recovering computations when such errors are detected. We analyze performance of data coding in GPUs and present optimizations geared toward memory-intensive GPU applications. We present performance studies of the prototype implementation of the framework and show that the proposed framework can be realized with negligible overheads in compute intensive applications such as N-body problem and matrix multiplication, and as low as 35% in a highly-efficient memory intensive 3-D FFT kernel.
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