3598

Parallel On-Chip Power Distribution Network Analysis on Multi-Core-Multi-GPU Platforms

Zhuo Feng, Zhiyu Zeng, Peng Li
Department of ECE, Michigan Technological University, Houghton
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2010)

@article{fengparallel,

   title={Parallel On-Chip Power Distribution Network Analysis on Multi-Core-Multi-GPU Platforms},

   author={Feng, Z. and Zeng, Z. and Li, P.},

   journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},

   number={99},

   pages={1–14},

   issn={1063-8210},

   publisher={IEEE}

}

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The challenging task of analyzing on-chip power (ground) distribution networks with multimillion node complexity and beyond is key to today’s large chip designs. For the first time, we show how to exploit recent massively parallel single-instruction multiple-thread (SIMT)-based graphics processing unit (GPU) platforms to tackle large-scale power grid analysis with promising performance. Several key enablers including GPU-specific algorithm design, circuit topology transformation, workload partitioning, performance tuning are embodied in our GPU-accelerated hybrid multigrid (HMD) algorithm (GpuHMD) and its implementation. We also demonstrate that using the HMD solver as a preconditioner, the conjugate gradient solver can converge much faster to the true solution with good robustness. Extensive experiments on industrial and synthetic benchmarks have shown that for DC power grid analysis using one GPU, the proposed simulation engine achieves up to 100 $times$ runtime speedup over a state-of-the-art direct solver and more than 50 $times$ speedup over the CPU based multigrid implementation, while utilizing a four-core-four-GPU system, a grid with eight million nodes can be solved within about 1 s. It is observed that the proposed approach scales favorably with the circuit complexity, at a rate about 1 s per two million nodes on a single GPU card.
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