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HPP-Controller: An intra-node controller designed for connecting heterogeneous CPUs

Qiang Li, Panyong Zhang, Ninghui Sun
Inst. of Comput. Technol., Nat. Res. Center for Intell. Comput. Syst., Chinese Acad. of Sci., Beijing, China
IEEE International Conference on Cluster Computing and Workshops, CLUSTER ’09, 2009

@conference{li2009hpp,

   title={HPP-Controller: An intra-node controller designed for connecting heterogeneous CPUs},

   author={Li, Q. and Zhang, P. and Sun, N.},

   booktitle={Cluster Computing and Workshops, 2009. CLUSTER’09. IEEE International Conference on},

   pages={1–4},

   issn={1552-5244},

   year={2009},

   organization={IEEE}

}

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Heterogeneity is considered as a solution for supercomputers to scale to petascale. Many systems which are composed of general CPUs and special processing units such as Cells, GPGPUs and FPGAs have been implemented. In these systems, CPU needs interact with special processing units to process data together, thus communications between these heterogeneous processing units become a key problem, and the communication subsytem should provide low latency and high bandwidth. In this paper, we propose HPP-Controller, which is designed for connecting two different types of CPUs (AMD and Loongson) in one node. It connects heterogeneous CPUs on top of no-coherent HyperTransport (HT) fabric and supports Global Physical Address Space. We implement a FPGA-based prototype and evaluate it via experiments. Initial results show that HPP-Controller has low latency of 0.75 us and high bandwidth close to bandwith of HT links.
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