3854

GPU-based time parallel cache simulator

Junjie Ma, Han Wan, Xiaopeng Gao, Xiang Long
State Key Lab. of Virtual Reality Technol. & Syst., Beihang Univ., Beijing, China
IEEE Youth Conference on Information Computing and Telecommunications (YC-ICT), 2010

@conference{ma2010gpu,

   title={GPU-based time parallel cache simulator},

   author={Ma, J. and Wan, H. and Gao, X. and Long, X.},

   booktitle={Information Computing and Telecommunications (YC-ICT), 2010 IEEE Youth Conference on},

   pages={407–410},

   organization={IEEE},

   year={2010}

}

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We present the design of time parallel trace-driven cache simulation for the purpose of evaluating different cache architectures. Due to the long simulation cycles, traditional sequential simulation methods are no longer practical. An obvious way to achieve fast parallel simulation is time parallel. It splits the whole trace into small slices which are assigned to parallel processors for concurrent simulation. In this paper, we introduce a novel time parallel multi-configuration simulation on single pass method. It exploits time partitioning as the main sources of parallelism and takes the full advantage of the computational capability offered by the Compute Unified Device Architecture (CUDA) on the GPU. Our experimental results demonstrate that the cache simulator based on GPU platform gains 1.91x performance improvement compared to traditional serial algorithm.
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