3975

A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization

Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala
Electr. & Comput. Eng., Utah State Univ., Logan, UT, USA
24th International Conference on VLSI Design (VLSI Design), 2011

@inproceedings{han2011gpu,

   title={A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization},

   author={Han, Y. and Chakraborty, K. and Roy, S. and Kuntamukkala, V.},

   booktitle={2011 24th Annual Conference on VLSI Design},

   pages={159–164},

   year={2011},

   organization={IEEE}

}

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In this paper, we propose a novel floor planning algorithm for GPUs. Floor planning is an inherently sequential algorithm, far from the typical programs suitable for Single Instruction Multiple Thread (SIMT) style concurrency in a GPU. We propose a fundamentally different approach of exploring the floor plan solution space, where we evaluate concurrent moves on a given floor plan. We illustrate several performance optimization techniques for this algorithm in GPUs. Compared to the sequential algorithm, our techniques achieve 4-30X speedup for a range of MCNC benchmarks, while delivering comparable or better solution quality.
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