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Analyzing throughput of GPGPUs exploiting within-die core-to-core frequency variation

Jungseob Lee, Paritosh Pratap Ajgaonkar, Nam Sung Kim
Department of Electrical and Computer Engineering, University of Wisconsin-Madison
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2011

@inproceedings{lee2011analyzing,

   title={Analyzing throughput of GPGPUs exploiting within-die core-to-core frequency variation},

   author={Lee, J. and Ajgaonkar, P.P. and Kim, N.S.},

   booktitle={Performance Analysis of Systems and Software (ISPASS), 2011 IEEE International Symposium on},

   pages={237–246},

   organization={IEEE},

   year={2011}

}

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The state-of-the-art general-purpose graphic processing units (GPGPUs) can offer very high computational throughput for general-purpose, highly-parallel applications using hundreds of available on-chip cores. Meanwhile, as technology is scaled down below 65nm, each core’s maximum frequency varies significantly due to increasing within-die variations. This, in turn, diminishes the throughput improvement of GPGPUs through technology scaling because the maximum frequency is often limited by the slowest core. In this paper, we investigate two techniques that can mitigate the impact of frequency variations on GPGPU’s throughput: 1) running each core at its maximum frequency independently and 2) disabling the slowest cores. Both can maximize GPGPU’s frequency at either the individual core or entire processor level. Our experimental results using a GPGPU simulator and a 32nm technology show that the first and second techniques can improve the throughput of compute- and problem-size-bounded applications by up to 32% and 19%, respectively.
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