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Coprocessor Computing with FPGA and GPU

Song Jun Park, Dale R. Shires, Brian J. Henz
Aberdeen Proving Ground, US Army Res. Lab. (ARL), Aberdeen, MD
DoD HPCMP Users Group Conference, 2008. DOD HPCMP UGC

@inproceedings{park2009coprocessor,

   title={Coprocessor Computing with FPGA and GPU},

   author={Park, S.J. and Shires, D.R. and Henz, B.J.},

   booktitle={DoD HPCMP Users Group Conference, 2008. DOD HPCMP UGC},

   pages={366–370},

   year={2009},

   organization={IEEE}

}

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Specialized secondary processing units, such as field programmable gate arrays (FPGAs) and graphics processing units (GPUs), attempt to tackle the time consuming applications containing high computational requirements. In order to achieve acceleration, FPGAs allow a customizable architecture and Nvidia GPUs offer up to 16 cores with 128 stream processors. The following research presents the experiences of designing integer and floating-point based algorithms for Xilinx FPGAs and programming on NVIDIA graphics card. For test case applications, an encryption function and a sorting algorithm were investigated. The implementation of an encryption algorithm depicts the performance results of an integer application composed of bit operations and a simple sort algorithm tests the effects of a floating-point application containing large numbers of multiple independent sorting instructions.
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