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Massively Parallel Finite Element Simulator for Full-Chip STI Stress Analysis

Jiying Xue, Xiaomeng Jiao, Yangdong Deng, Hao Qian, Dajie Zeng, Guoyu Li, Zhiping Yu
Inst. of Microelectron., Tsinghua Univ., Beijing, China
IEEE 10th International Conference on Computer and Information Technology (CIT), 2010

@inproceedings{xue2010massively,

   title={Massively Parallel Finite Element Simulator for Full-Chip STI Stress Analysis},

   author={Xue, J. and Jiao, X. and Deng, Y. and Qian, H. and Zeng, D. and Li, G. and Yu, Z.},

   booktitle={Computer and Information Technology (CIT), 2010 IEEE 10th International Conference on},

   pages={1196–1201},

   year={2010},

   organization={IEEE}

}

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In modern integrated circuit (IC) designs with feature size finer than 90nm, the stress among different material layers is playing an important role in determining device performance. The stress can be classified into two categories, stress deliberately introduced during semiconductor process, and stress unintentionally formed through the synergy of different processing steps. Among different types of inadvertent stresses, Shallow trench isolation (STI) stress which is exerted from the isolation materials is the primary one that has a major impact on circuit characteristics. A detailed analysis of STI stress on an IC chip, however, is a complicated process because the stress is determined by the distribution of layout patterns, which could add up to trillions in today’s typical IC designs. The traditional technology computer aided design (TCAD) tools for such an analysis are already too slow on large circuits. In this work, a GPU-based finite element simulator for full chip stress analysis is developed. Experimental results showed that the GPU-based simulator could outperform its CPU equivalent by a factor of 20X. Such a speedup would allow detailed stress-aware performance optimization for large ICs.
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