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Parallel multi-level analytical global placement on graphics processing units

Jason Cong, Yi Zou
Computer Science Department, University of California, Los Angeles, CA 90095, USA
IEEE/ACM International Conference on Computer-Aided Design – Digest of Technical Papers, 2009. ICCAD 2009

@inproceedings{cong2009parallel,

   title={Parallel multi-level analytical global placement on graphics processing units},

   author={Cong, J. and Zou, Y.},

   booktitle={Proceedings of the 2009 International Conference on Computer-Aided Design},

   pages={681–688},

   year={2009},

   organization={ACM}

}

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GPU platforms are becoming increasingly attractive for implementing accelerators because they feature a larger number of cores with improved programmability. In this paper, we describe our implementation of a state-of-the-art academic multi-level analytical placer mPL on Nvidia’s massively parallel GT200 series platforms. We detail our efforts on performance tuning and optimizations. When compared to software implementation on Intel’s recent generation Xeon CPU, the speed of the global placement part of mPL is 15x faster on average using a Tesla C1060 card, with comparable WL. (less than 1% WL degradation on average).
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