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A low-power integrated x86-64 and graphics processor for mobile computing devices

S.R. Gutta, D. Foley, A. Naini, R. Wasmuth, D. Cherepacha
AMD, Hyderabad, India
IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011

@inproceedings{gutta2011low,

   title={A low-power integrated x86-64 and graphics processor for mobile computing devices},

   author={Gutta, S.R. and Foley, D. and Naini, A. and Wasmuth, R. and Cherepacha, D.},

   booktitle={IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011},

   pages={270–272},

   year={2011},

   organization={IEEE}

}

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AMD’s first Fusion Accelerated Processor Unit (APU) codenamed "Zacate" combines a pair of x86 CPUs cores codenamed "Bobcat", 1MB L2 Cache, Client Northbridge (CNB), with a DirectX" 11 Radeon HD5000 graphics/multimedia controller on a single die. The CNB provides an interface to a sin gle 64b DDR3 memory channel, which can operate at up to DDR3-1066. The Fusion architecture implements an efficient form of unified memory architecture (UMA) where a portion of system memory is reserved as graphics frame buffer memory. The graphics memory controller (GMC) arbitrates between graphics, video and display memory accesses and presents a well-ordered stream of sys tem memory requests through the CNB over dedicated 256b wide read and write busses. These GMC requests bypass all of the CNB coherency mechanisms allowing for fast direct access to memory and exposing most of the available memory bandwidth (8.53GB/S). Compared to two chip solutions, use of the on die integrated GPU significantly reduces memory latency, improves request ordering, and reduces power The APU supports display formats including VGA, LVDS, Display Port, DVI or HDMI. A x4 Gen2 PCIe Unified Media Interface (UMI) to an external Fusion Controller Hub (FCH) is supported for system I/O. An additional 4x PCIe Gen2 link supports I/O to external Discrete Graphics chip.
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