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Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs)

Doris Chen, Deshanand Singh
University of Toronto, Toronto, ON, Canada
International Conference on Field Programmable Logic and Applications (FPL), 2010

@inproceedings{chen2010parallelizing,

   title={Parallelizing FPGA Technology Mapping using Graphics Processing Units (GPUs)},

   author={Chen, D. and Singh, D.},

   booktitle={2010 International Conference on Field Programmable Logic and Applications},

   pages={125–132},

   year={2010},

   organization={IEEE}

}

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GPUs are becoming an increasingly attractive option for obtaining performance speedups for data-parallel applications. FPGA technology mapping is an algorithm that is heavily data parallel; however, it has many features that make it unattractive to implement on a GPU. The algorithm uses data in irregular ways since it is a graph-based algorithm. In addition, it makes heavy use of constructs like recursion which is not supported by GPU hardware. In this paper, we take a state-of-the-art FPGA technology mapping algorithm within Berkeley’s ABC package and attempt to parallelize it on a GPU. We show that runtime gains of 3.1x are achievable while maintaining identical quality as demonstrated by running these netlists through Altera’s Quartus II place-and-route tool.
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