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EQUIPE: Parallel equivalence checking with GP-GPUs

Debapriya Chatterjee, Valeria Bertacco
Department of Computer Science and Engineering, University of Michigan, Ann Arbor, MI, USA
IEEE International Conference on Computer Design (ICCD), 2010

@inproceedings{chatterjee2010equipe,

   title={EQUIPE: Parallel equivalence checking with GP-GPUs},

   author={Chatterjee, D. and Bertacco, V.},

   booktitle={Computer Design (ICCD), 2010 IEEE International Conference on},

   pages={486–493},

   organization={IEEE},

   year={2010}

}

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Combinational equivalence checking (CEC) is a mainstream application in Electronic Design Automation used to determine the equivalence between two combinational netlists. Tools performing CEC are widely deployed in the design flow to determine the correctness of synthesis transformations and optimizations. One of the main limitations of these tools is their scalability, as industrial scale designs demand time-consuming computation. In this work we propose EQUIPE, a novel combinational equivalence checking solution, which leverages the massive parallelism of modern general purpose graphic processing units. EQUIPE reduces the need for hard-to-parallelize engines, such as BDDs and SAT, by taking advantage of algorithms well-suited to concurrent implementation. We found experimentally that EQUIPE outperforms commercial CEC tools by an order of magnitude, on average, and state-of-the-art research CEC solutions by up to a factor of three, on a wide range of industry-strength designs.
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