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PIR: PMaC’s Idiom Recognizer

Catherine Olschanowsky, Allan Snavely, Mitesh R. Meswani, Laura Carrington
Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA, USA
39th International Conference on Parallel Processing Workshops (ICPPW), 2010

@inproceedings{olschanowsky2010pir,

   title={PIR: PMaC’s Idiom Recognizer},

   author={Olschanowsky, C. and Snavely, A. and Meswani, M.R. and Carrington, L.},

   booktitle={2010 39th International Conference on Parallel Processing Workshops},

   pages={189–196},

   year={2010},

   organization={IEEE}

}

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The speed of the memory subsystem often constrains the performance of large-scale parallel applications. Experts tune such applications to use hierarchical memory subsystems efficiently. Hardware accelerators, such as GPUs, can potentially improve memory performance beyond the capabilities of traditional hierarchical systems. However, the addition of such specialized hardware complicates code porting and tuning. During porting and tuning expert application engineers manually browse source code and identify memory access patterns that are candidates for optimization and tuning. HPC applications typically contain thousands to hundreds of thousands of lines of code, creating a labor-intensive challenge for the expert. PIR, PMaC’s Static Idiom Recognizer, automates the pattern recognition process. PIR recognizes specified patterns and tags the source code where they appear using static analysis. This paper describes the PIR implementation and defines a subset of idioms commonly found in HPC applications. We examine the effectiveness of the tool, demonstrating 95% identification accuracy and present the results of using PIR on two HPC applications.
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