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An algorithm-architecture co-design framework for gridding reconstruction using FPGAs

Srinidhi Kestur, Kevin Irick, Sungho Park, Ahmed Al Maashri, Vijaykrishnan Narayanan, Chaitaili Chakrabarti
Dept of Computer Science and Engineering, The Pennsylvania State University, USA
48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011

@article{kestur2011algorithm,

   title={An Algorithm-Architecture Co-design Framework for Gridding Reconstruction using FPGAs},

   author={Kestur, S. and Irick, K. and Park, S. and Al Maashri, A. and Narayanan, V. and Chakrabarti, C.},

   year={2011}

}

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Gridding is a method of interpolating irregularly sampled data on to a uniform grid and is a critical image reconstruction step in several applications which operate on non-Cartesian sampled data. In this paper, we present an algorithm-architecture co-design framework for accelerating gridding using FPGAs. We present a parameterized hardware library for accelerating gridding to support both arbitrary and regular trajectories. We further describe our kernel automation framework which supports several kernel functions through look-up-table (LUT) based Taylor polynomial evaluation. This framework is integrated using an in-house multi-FPGA development platform which provides hardware infrastructure for integrating custom accelerators. Design-space exploration is enabled by an automation flow which allows system generation from an algorithm specification. We further provide several case studies by realizing systems for nonuniform fast Fourier transform (NuFFT) with different parameter sets and porting them on to the BEE3 platform. Results show speedups of more than 16X and 2X over existing CPU and FPGA implementations respectively, and up to 5.5 times higher performance-per-watt over a comparable GPU implementation.
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