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Early experiences with the intel many integrated cores accelerated computing technology

L. Koesterke, J. Boisseau, J. Cazes, K. Milfeld, D. Stanzione
The University of Texas at Austin
Proceedings of the 2011 TeraGrid Conference: Extreme Digital Discovery, TG ’11, 2011

@inproceedings{Koesterke:2011:EEI:2016741.2016764,

   author={Koesterke, L. and Boisseau, J. and Cazes, J. and Milfeld, K. and Stanzione, D.},

   title={Early experiences with the intel many integrated cores accelerated computing technology},

   booktitle={Proceedings of the 2011 TeraGrid Conference: Extreme Digital Discovery},

   series={TG ’11},

   year={2011},

   isbn={978-1-4503-0888-5},

   location={Salt Lake City, Utah},

   pages={21:1–21:8},

   articleno={21},

   numpages={8},

   url={http://doi.acm.org/10.1145/2016741.2016764},

   doi={http://doi.acm.org/10.1145/2016741.2016764},

   acmid={2016764},

   publisher={ACM},

   address={New York, NY, USA},

   keywords={accelerated computing, programming models}

}

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We report on early programming experiences with the Intel Many Integrated Core (Intel MIC) Co-processor. This new and x86 based technology is Intel’s answer to GPU-based accelerators by NVIDIA, AMD and others. Accelerators have generally sparked interest in the HPC community because they have the potential to significantly increase the compute power of the next generation of supercomputers. The merits of accelerators for general HPC purposes are still very much under debate. Undoubtedly accelerators add more complexity to an already very complex cluster, and the programmability of accelerators will be the key to enticing the diverse HPC user community to this new technology, even if the performance promise may be large. The study presented here is part of a much broader activity at the Texas Advanced Computing Center (TACC) that focuses on a wide range of accelerators (GPUs, FPGAs, Intel MIC coprocessor, etc.). The Intel MIC architecture is x86 based and supports languages and parallel programming paradigms commonly found on x86 CPUs, including OpenMP which has been widely accepted in the HPC community for thread-parallel programming. The scope of this initial study is limited to the investigation of the Intel MIC programming environment and particularly to the offload-OpenMP model. Our initial experience with the Intel MIC platform has been very positive. The required code modifications to handle the data transfer and the offloading of parallel sections onto the Intel MIC co-processor are small and conveniently implemented as directives/pragmas to OpenMP constructs. (We use "accelerators" as a generic reference to Intel MIC Co-processors, GPUs, FPGAs, etc.)
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