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Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing

James Coole, Greg Stitt
Department of Electrical & Computer Engineering, University of Florida, Gainesville, FL, USA
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES/ISSS ’10, 2010

@inproceedings{coole2010intermediate,

   title={Intermediate fabrics: Virtual architectures for circuit portability and fast placement and routing},

   author={Coole, J. and Stitt, G.},

   booktitle={Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis},

   pages={13–22},

   year={2010},

   organization={ACM}

}

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Although hardware/software partitioning of embedded applications onto FPGAs is widely known to have performance and power advantages, FPGA usage has been typically limited to hardware experts, due largely to several problems: 1) difficulty of integrating hardware design tools into well-established software tool flows, 2) increasingly lengthy FPGA design iterations due to placement and routing, and 3) a lack of portability and interoperability resulting from device/platform-specific tools and bitfiles. In this paper, we directly address the last two problems by introducing intermediate fabrics, which are virtual reconfigurable architectures specialized for different application domains, implemented on top of commercial-off-the-shelf devices. Such specialization enables near-instantaneous placement and routing by hiding the complexity of fine-grained physical devices, while also enabling circuit portability across all devices that implement the intermediate fabric. When combined with existing work on runtime synthesis from software binaries, intermediate fabrics reduce the effects of all three problems by enabling transparent usage of COTS FPGAs by software designers. In this paper, we explore intermediate fabric architectures using specialization techniques to minimize area and performance overhead of the virtual fabric while maximizing routability and speedup of placement and routing. We present results showing an average placement and routing speedup of 554x, with an average area overhead of 10% and clock overhead of 18%, which corresponds to an average frequency of 195 MHz.
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