5590

Programmable and Scalable Architecture for Graphics Processing Units

Carlos S. de La Lama, Pekka Jaaskelainen, Jarmo Takala
Universidad Rey Juan Carlos, Department of Computer Architecture, Computer Science and Artificial Intelligence
Embedded Computer Systems: Architectures, Modeling, and Simulation, Lecture Notes in Computer Science, 2009, Volume 5657/2009, 2-11

@article{de2009programmable,

   title={Programmable and Scalable Architecture for Graphics Processing Units},

   author={de La Lama, C. and J{\"a}{\"a}skel{\"a}inen, P. and Takala, J.},

   journal={Embedded Computer Systems: Architectures, Modeling, and Simulation},

   pages={2–11},

   year={2009},

   publisher={Springer}

}

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Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high performance floating point processing and application specific hardware stages for maximizing the graphics throughput. In this paper we evaluate the suitability of Transport Triggered Architectures (TTA) as a basis for implementing GPUs. TTA improves scalability over the traditional VLIW-style architectures making it interesting for computationally intensive applications. We show that TTA provides high floating point processing performance while allowing more programming freedom than vector processors. Finally, one of the main features of the presented TTA-based GPU design is its fully programmable architecture making it suitable target for general purpose computing on GPU APIs which have become popular in recent years.
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