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High-Level Synthesis for FPGAs: From Prototyping to Deployment

Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees Vissers, Zhiru Zhang
AutoESL Design Technologies, Inc., Los Angeles, CA 90064 USA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011

@article{cong2011high,

   title={High-Level Synthesis for FPGAs: From Prototyping to Deployment},

   author={Cong, J. and Liu, B. and Neuendorffer, S. and Noguera, J. and Vissers, K. and Zhang, Z.},

   journal={Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},

   volume={30},

   number={4},

   pages={473–491},

   year={2011},

   publisher={IEEE}

}

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Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS msystem-on-chip design complexityethodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL’s AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.
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