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Low Latency Complex Event Processing on Parallel Hardware

Gianpaolo Cugola, Alessandro Margara
Dip. di Elettronica e Informazione, Politecnico di Milano, Italy
Politecnico di Milano, Technical Report, 2011

@techreport{cugola2011low,

   title={Low Latency Complex Event Processing on Parallel Hardware},

   author={Cugola, G. and Margara, A.},

   year={2011},

   institution={Technical report, Politecnico di Milano}

}

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Several application domains involve observing events, processing them, and reacting. This asks for a Complex Event Processing (CEP) engine in charge of interpreting, filtering, and combining primitive events that occur in the external environment, to identify higher level composite events, according to a set of rules written in an ad-hoc rule definition language. A key requirement for a CEP engine is low latency processing, even in presence of complex rules and large numbers of incoming events. In this paper we investigate how a CEP engine may take advantage of parallel hardware to speed up processing. In particular, we consider the most common operators offered by existing rule languages (i.e., sequences, parameters, and aggregates); we define different algorithms to process rules built using such operators; and we discuss how they can be implemented on a multi-core CPU and on CUDA, a widespread architecture for general purpose programming on GPUs. On one hand our analysis demonstrates that the use of GPUs can bring impressive speedups in presence of complex rules. On the other hand, it shows that multi-core CPUs scale better with the number of rules.
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