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Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors

V. Saripalli, G. Sun, A. Mishra, Y. Xie, S. Datta, V. Narayanan
Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2011

@article{saripalli2011exploiting,

   title={Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors},

   author={Saripalli, V. and Sun, G. and Mishra, A. and Xie, Y. and Datta, S. and Narayanan, V.},

   journal={Emerging and Selected Topics in Circuits and Systems, IEEE Journal on},

   volume={1},

   number={2},

   pages={109–119},

   year={2011},

   publisher={IEEE}

}

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Heterogeneous multicores are envisioned to be a promising design paradigm to combat today’s challenges of power, memory, and reliability walls that are impeding chip design using deep submicron technology. Future multicores are expected to integrate multiple different cores, including GPGPUs, custom accelerators and configurable cores. In this paper, we introduce an important dimension-technology-using which heterogeneity can be introduced in multicores to improve their energy-performance envelope. Specifically, we analyze the benefits of heterogenous technologies for processor cores and cache subsystems. We discuss two promising device candidates (Tunnel-FET and Magnetic-RAM) for introducing technological diversity in the multicores and analyze their integration in the processor and cache hierarchy in detail. Our analysis shows that introducing such a kind of heterogeneity can significantly enhance the performance and energy behavior of future multicore systems.
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