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DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function

Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, Jinwoo Shin
School of Computer Science, Georgia Institute of Technology
IEEE Computer Architecture Letters, 2011

@article{lakshminarayana2011dram,

   title={DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function},

   author={Lakshminarayana, N.B. and Lee, J. and Kim, H. and Shin, J.},

   journal={IEEE IEEE Computer Architecture Letters},

   year={2011},

   publisher={Published by the IEEE Computer Society}

}

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GPGPU architectures (applications) have several different characteristics compared to traditional CPU architectures (applications): highly multithreaded architectures and SIMD-execution behavior are the two important characteristics of GPGPU computing. In this paper, we propose a potential function that models the DRAM behavior in GPGPU architectures and a DRAM scheduling policy, Alpha-SJF policy to minimize the potential function. The scheduling policy essentially chooses between SJF and FR-FCFS at run-time based on the number of requests from each thread and whether the thread has a row buffer hit.
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