6943

FPGA Based Acceleration of Decimal Operations

Alberto Nannarelli
Dept. Informatics and Mathematical Modelling, Technical University of Denmark, Kongens Lyngby, Denmark
2011 International Conference on Reconfigurable Computing and FPGAs, 2011

@inproceedings{nannarelli2011fpga,

   title={FPGA Based Acceleration of Decimal Operations},

   author={Nannarelli, A.},

   booktitle={2011 International Conference on Reconfigurable Computing and FPGAs},

   pages={146–151},

   year={2011},

   organization={IEEE}

}

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Field Programmable Gate-Arrays (FPGAs) can efficiently implement application specific processors in non-conventional number systems, such as the decimal (Binary-Coded Decimal, or BCD) number system required for accounting accuracy in financial applications. The main purpose of this work is to show that applications requiring several decimal (BCD) operations can be accelerated by a processor implemented on a FPGA board connected to the computer by a standard bus. For the case of a telephone billing application, we demonstrate that even a basic implementation of the decimal processor on the FPGA, without an advanced input/output interface, can achieve a speed-up of about 10 over its execution on the CPU of the hosting computer.
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