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Parallel Symbolic Analysis of Large Analog Circuits on GPU Platforms

Sheldon X.-D. Tan, Xue-Xin Liu, Eric Mlinar and Esteban Tlelo-Cuautle
Department of Electrical Engineering, University of California, Riverside, CA 92521
VLSI Design, ISBN: 978-953-307-884-7, InTech, 2012

@article{sheldon2012parallel,

   title={Parallel Symbolic Analysis of Large Analog Circuits on GPU Platforms},

   author={Sheldon, XD and Liu, X.X. and Mlinar, E. and Tlelo-Cuautle, E.},

   year={2012}

}

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Graph-based symbolic technique is a viable tool for calculating the behavior or the characterization of an analog circuit. Traditional symbolic analysis tools typically are used to calculate the behavior or the characteristic of a circuit in terms of symbolic parameters (Gielen et al., 1994). The introduction of determinant decision diagrams based symbolic analysis technique allows exact symbolic analysis of much larger analog circuits than any other existing approaches (Shi & Tan, 2000; 2001). Furthermore, with hierarchical symbolic representations (Tan et al., 2005; Tan & Shi, 2000), exact symbolic analysis via DDD graphs essentially allows the analysis of arbitrarily large analog circuits. Some recent advancement in DDD ordering technique and variants of DDD allow even larger analog circuits to be analyzed (Shi, 2010a;b). Once the circuit’s small-signal characteristics are presented by DDDs, the evaluation of DDDs, whose CPU time is proportional to the sizes of DDDs, will give exact numerical values. However, with large networks, the DDD size can be huge and the resulting evaluation can be very time consuming.
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