Systematic construction, verification and implementation methodology for LDPC codes
Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai, P. R. China
EURASIP Journal on Wireless Communications and Networking, 2012:84, 2012
@article{yu2012systematic,
title={Systematic construction, verification and implementation methodology for LDPC codes},
author={Yu, H. and Cui, J. and Wang, Y. and Yang, Y.},
journal={EURASIP Journal on Wireless Communications and Networking},
volume={2012},
number={1},
pages={84},
year={2012},
publisher={Springer}
}
In this article, a novel and systematic Low-density parity-check (LDPC) code construction, verification and implementation methodology is proposed. The methodology is composed by the simulated annealing based LDPC code constructor, the GPU based high-speed code selector, the ant colony optimization based pipeline scheduler and the FPGA-based hardware implementer. Compared to the traditional ways, this methodology enables us to construct both decoding performance-aware and hardware-efficiency-aware LDPC codes in a short time. Simulation results show that the generated codes have much less cycles (length 6 cycles eliminated) and memory conflicts (75% reduction on idle clocks), while having no BER performance loss compared to WiMAX codes. Additionally, the simulation speeds up by 490 times under float precision against CPU and a net throughput 24.5 Mbps is achieved. Finally, a net throughput 1.2 Gbps (bit-throughput 2.4 Gbps) multi-mode LDPC decoder is implemented on FPGA, with completely on-the-fly configurations and less than 0.2 dB BER performance loss.
March 28, 2012 by hgpu
