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A Programmable Processing Array Architecture Supporting Dynamic Task Scheduling and Module-Level Prefetching

Junghee Lee, Hyung Gyu Lee, Soonhoi Ha, Jongman Kim, Chrysostomos Nicopoulos
Georgia Institute of Technology, 777 Atlantic Dr NW, Atlanta, GA 30332, USA
The ACM International Conference on Computing Frontiers, 2012

@article{lee2012programmable,

   title={A Programmable Processing Array Architecture Supporting Dynamic Task Scheduling and Module-Level Prefetching},

   author={Lee, J. and Lee, H.G. and Ha, S. and Kim, J. and Nicopoulos, C.},

   year={2012}

}

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Massively Parallel Processing Arrays (MPPA) constitute programmable hardware accelerators that excel in the execution of applications exhibiting Data-Level Parallelism (DLP). The concept of employing such programmable accelerators as sidekicks to the more traditional, general-purpose processing cores has very recently entered the mainstream; both Intel and AMD have introduced processor architectures integrating a Graphics Processing Unit (GPU) alongside the main CPU cores. These GPU engines are expected to play a pivotal role in the espousal of General-Purpose computing on GPUs (GPGPU). However, the widespread adoption of MPPAs, in general, as hardware accelerators entails the effective tackling of some fundamental obstacles: the expressiveness of the programming model, the debugging capabilities, and the memory hierarchy design. Toward this end, this paper proposes a hardware architecture for MPPA that adopts an event-driven execution model. It supports dynamic task scheduling, which offers better expressiveness to the execution model and improves the utilization of processing elements. Moreover, a novel module-level prefetching mechanism – enabled by the specification of the execution model – hides the access time to memory and the scheduler. The execution model also ensures complete encapsulation of the modules, which greatly facilitates debugging. Finally, the fact that all associated inputs of a module are explicitly known can be exploited by the hardware to hide memory access latency without having to resort to caches and a cache coherence protocol. Results using a cycle-level simulator of the proposed architecture and a variety of real application benchmarks demonstrate the efficacy and efficiency of the proposed paradigm.
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