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Effective Sparse Matrix Representation for the GPU Architectures

B. Neelima, Prakash S. Raghavendra
National Institute of Technology, Karnataka
International Journal of Computer Science, Engineering and Applications (IJCSEA), Volume 2, Number 2, 2012

@article{neelima2012effective,

   title={Effective Sparse Matrix Representation for the GPU Architectures},

   author={Neelima, B. and Raghavendra, P.S.},

   year={2012}

}

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General purpose computation on graphics processing unit (GPU) is prominent in the high performance computing era of this time. Porting or accelerating the data parallel applications onto GPU gives the default performance improvement because of the increased computational units. Better performances can be seen if application specific fine tuning is done with respect to the architecture under consideration. One such very widely used computation intensive kernel is sparse matrix vector multiplication (SPMV) in sparse matrix based applications. Most of the existing data format representations of sparse matrix are developed with respect to the central processing unit (CPU) or multi cores. This paper gives a new format for sparse matrix representation with respect to graphics processor architecture that can give 2x to 5x performance improvement compared to CSR (compressed row format), 2x to 54x performance improvement with respect to COO (coordinate format) and 3x to 10 x improvement compared to CSR vector format for the class of application that fit for the proposed new format. It also gives 10% to 133% improvements in memory transfer (of only access information of sparse matrix) between CPU and GPU. This paper gives the details of the new format and its requirement with complete experimentation details and results of comparison.
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